1. Field of the Invention
The present invention relates to a structure for improving a performance of transistors of the same type formed in a common chip, and also relates to a method for manufacturing the same.
2. Description of the Background Art
FIG. 32 shows known transistors (conventional N-channel or P-channel transistors), which are of the same type and have different thresholds, and particularly shows a cross section taken along line extending lengthwise through gates. FIG. 32 shows, from the left, transistors having smallest to largest thresholds, i.e., a transistor forming a sense amplifier, a transistor forming a peripheral circuit and a transistor forming a memory cell.
In FIG. 32, a reference number 101 indicates a semiconductor substrate, 102 indicates an LOCOS (Local Oxidation of Silicon) isolating and insulating film, and 103 indicates a heavily doped layer for preventing punch through. A reference number 104 indicates a first impurity layer which is formed at a channel region A in an MIS (Metal Insulator Semiconductor) transistor forming a sense amplifier, and is located at a predetermined depth from a main surface of semiconductor substrate 101. A reference number 105 indicates a second impurity layer which is formed at a channel region B in an MIS transistor forming a peripheral circuit, and is located at a predetermined depth from a main surface of semiconductor substrate 101. A reference number 106 indicates a third impurity layer which is formed at a channel region C in an MIS transistor forming a memory cell, and is located at a predetermined depth from a main surface of semiconductor substrate 101.
In FIG. 32, a reference number 107 indicates a gate insulating film which is formed at the main surface of semiconductor substrate 101 and is made of a silicon oxide film or the like. 108 indicates a gate electrode which is formed on gate insulating film 107, and is made of an electrically conductive film of, e.g., doped polycrystalline silicon. 109 indicates a side wall which is formed of an insulating film on a side surface of gate electrode 109. Reference numbers 110 indicate source/drain regions of an LDD (Lightly Doped Drain) structure formed by diffusing impurity of a conductivity type opposite to that of the channel impurity layer.
First, second and third impurity layers 104, 105 and 106 shown in FIG. 32 are formed at positions spaced from the main surface of semiconductor substrate 101 by predetermined distances depending on only the types of transistors, respectively. The impurity layer for the transistor which should have a larger threshold has a larger impurity concentration, and in other words, the impurity concentration of the impurity layer for the sense amplifier is smaller than that for the peripheral circuit, which is smaller than that for the memory cell. By employing the impurity layers of different impurity concentrations for forming channel regions A, B and C, the thresholds can be controlled such that first impurity layer 104 having a large impurity concentration has a small threshold, and third impurity layer 106 having a small impurity concentration has a large threshold.
FIGS. 33 to 35 show impurity concentration profiles on sections XXXIII--XXXIII, XXXIV--XXXIV and XXXV--XXXV in FIG. 32 extending downward in a depth direction from the main surface of semiconductor substrate 101 of MIS transistors, respectively. More specifically, FIG. 33 shows an impurity concentration distribution in a depth direction at channel region A in the transistor for sense amplifier. This distribution exhibits a peak provided by first impurity layer 104 and another peak at a deeper position provided by heavily doped layer 103. Likewise, the impurity concentration distributions of the peripheral circuit and the memory cell are shown in FIGS. 34 and 35, respectively. The peak provided by second impurity layer 105 in the peripheral circuit is located at the same depth as first impurity layer 104, and exhibits a larger impurity concentration than that by first impurity layer 104. The peak provided by third impurity layer 106 in the memory cell is located at the same depth as those by first and second impurity layers 104 and 105, and exhibits a larger impurity concentration than those by first and second impurity layers 104 and 105.
For reference purposes, an impurity concentration profile by source/drain region 110 is shown, as an example, in FIG. 35. Since an impurity diffusion layer forming source/drain region 110 is not present immediately under gate electrode 108 in FIG. 32, FIG. 35 shows impurity concentration profiles taken on section XXXV--XXXVV extending through source/drain region 110 of the transistor for memory cell in FIG. 32. In FIG. 35, junction is formed at a position where the impurity curve of the channel region intersects the impurity curve of source/drain region 110 of the opposite conductivity type.
A method of manufacturing the above conventional semiconductor device will be described below. First, as shown in FIG. 36, thermal oxidation is effected to form LOCOS isolating and insulating film 102 on each region which will form an inactive region in P-type semiconductor substrate 101. Then, wells are formed by selectively ion-implanting ions into regions for forming the N-type transistors under conditions of 500 KeV and 5E12 cm.sup.-2. Thereafter, selective ion-implantation of, e.g., boron is performed under conditions of 100 KeV and 5E12 cm.sup.-2 to form heavily doped layer 103 for isolation immediately under each LOCOS isolating oxide film 102. simultaneously with this, heavily doped layers 103 are formed under channel regions A, B and C.
Then, as shown in FIG. 37, boron is ion-implanted into the whole surface of semiconductor substrate 101 under conditions of 50 KeV and 2E12 cm.sup.-2, whereby first impurity layer 104 of the transistor for sense amplifier is formed. Simultaneously with the formation of first impurity layer 104, first impurity layers 104 are formed at channel regions B and C of the transistors for peripheral circuit and memory cell.
As shown in FIG. 38, a resist pattern 111 is formed over the regions for transistors of a different type (P-channel transistors), the region of the transistor for sense amplifier and LOCOS isolating and insulating films 102 around the same, and boron is implanted into the regions for transistors for the peripheral circuit and memory cell under conditions of 50 KeV and 3E12 cm.sup.-2. Further, impurity is implanted into channel region B of the peripheral circuit to form second impurity layer 105 having a larger impurity concentration than first impurity layer 104. Thereby, channel region C of the transistor for memory cell has the same concentration as second impurity layer 105.
As shown in FIG. 39, a resist pattern 112 is formed over regions other than the region for forming the transistor for memory cell. Using resist pattern 112 as a mask, ion implantation of boron is performed under conditions of 50 KeV and 2E12 cm.sup.-2 for additionally introducing impurity into channel region C, so that third impurity layer 106 having a larger impurity concentration than second impurity layer 105 is formed.
In the conventional manufacturing method, as described above, first, second and third impurity layers 104, 105 and 106 are formed in the following manner. Ion implantation is performed several times for the heavily doped layer(s), and is performed one (or two) time(s) for the lightly doped layer(s), and all of the first and succeeding ion implanting operations are effected on positions at the same depth with the same implantation energy.
Japanese Patent Laying-Open No. 2-153574 (1990) has disclosed a technique similar to the above, and more specifically has disclosed the following technique. In transistors which have different thresholds but are of the same type, channel impurity layers having different impurity concentrations are formed at the same depth from a main surface of a semiconductor substrate. For forming causing a difference in impurity concentrations of the channel impurity layers, implantation is performed several times on a channel portion (at the same position) of a transistor(s) to be doped heavily.
According to the above structure, however, it is now required to increase impurity concentration for suppressing punch through, because channel lengths of transistors have been reduced in accordance with miniaturization of elements. Therefore, if channel implanting operations for three regions for the sense amplifier, peripheral circuit and memory cell were performed with the same energy, impurity concentrations would unpreferably increase at transistor surfaces of the regions for the sense amplifier and peripheral circuit, so that thresholds would unpreferably increase. In addition to this, since the impurity concentration is large at the channel region in the region for memory cell, the concentration is large at the junction between the source/drain region and the channel region, so that an excessively strong junction electric field is produced, and a junction leakage current increases.